SH7065 Datasheet, PDF (185/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Exception Handling Types and Priority
As table 5.1 indicates, exception handling may be caused by a reset, address error, interrupt, or
instruction. Exception handling is prioritized as shown in table 5.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority.
Table 5.1 Exception Types and Priority
Exception Handling
Priority
Reset
Power-on reset
High
Address errors CPU address error
DMAC address error
Interrupts
NMI
User break
External interrupt (IRQ/IRL)
On-chip peripheral Direct memory access controller (DMAC)
modules
Bus state controller (BSC)
Watchdog timer (WDT)
Timer pulse unit (TPU)
Serial communication interface (SCI)
Compare match timer (CMT)
A/D converter (A/D)
Motor management timer (MMT)
Instructions
Trap instruction (TRAPA instruction)
General illegal instruction (undefined code)
Slot illegal instruction (undefined code or instruction that modifies
PC^*1 located immediately after delayed branch instruction^*2)
Low
Notes: 1. Instructions that modify PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S,
BT/S, BSRF, BRAF
2. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 5.00 Sep 11, 2006 page 163 of 916
REJ09B0332-0500