SH7065 Datasheet, PDF (351/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
transfer. The flag clear timing select bit (FCS) in the channel control register (CHCR) is used to
select the transfer request signal clearing mode.
Table 9.4 Selecting On-Chip Peripheral Module Request Mode with RS Bits
DMAC
Transfer
Request
RS4 RS3 RS2 RS1 RS0 Source
0 1 0 0 0 TPU
DMAC Transfer Request
Signal
TGI0A interrupt
Transfer
Source
Any^*
1 TPU
TGI1A interrupt
Any^*
1 0 TPU
TGI2A interrupt
Any^*
1 TPU
TGI3A interrupt
Any^*
1 0 0 TPU
TGI4A interrupt
Any^*
1 TPU
TGI5A interrupt
Any^*
1 0 A/D
ADI0 (A/D conversion end ADDR0
converter interrupt)
1 A/D
ADI1 (A/D conversion end ADDR1
converter interrupt)
1 0 0 0 0 SCI0
TXI0 (SCI0 transmit-data- Any^*
transmitter empty transfer request)
1 SCI0
RXI0 (SCI0 receive-data-full RDR0
receiver transfer request)
1 0 SCI1
TXI1 (SCI1 transmit-data- Any^*
transmitter empty transfer request)
1 SCI1
RXI1 (SCI1 receive-data-full RDR1
receiver transfer request)
1 0 0 SCI2
TXI2 (SCI2 transmit-data- Any^*
transmitter empty transfer request)
10
1 SCI2
RXI2 (SCI2 receive-data-full RDR2
receiver transfer request)
0 MMT
TGM
Any^*
1 MMT
TGN
Any^*
Legend:
TPU:
SCI0, SCI1, SCI2:
Timer pulse unit
Serial communication interface channels 0 to 2
Transfer
Destina-
tion
Any^*
Any^*
Any^*
Any^*
Any^*
Any^*
Any^*
Any^*
TDR0
Any^*
TDR1
Any^*
TDR2
Any^*
Any^*
Any^*
Bus Mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Rev. 5.00 Sep 11, 2006 page 329 of 916
REJ09B0332-0500