SH7065 Datasheet, PDF (473/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.53 shows the timing in this case.
TGR write cycle
T1 T2
Pφ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10.53 Contention between TGR Write and Input Capture
Rev. 5.00 Sep 11, 2006 page 451 of 916
REJ09B0332-0500