SH7065 Datasheet, PDF (11/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

4.14 Module Clock Division Function ...................................................................................... 157
4.14.1 Clock Definitions ................................................................................................. 157
4.14.2 Transition to Module Clock Division Function.................................................... 158
4.14.3 Exit from Module Clock Division Function......................................................... 160
4.14.4 Notes on Use of Module Clock Division Function .............................................. 160
4.15 Note on Initialization......................................................................................................... 161
Section 5 Exception Handling ......................................................................................... 163
5.1 Overview........................................................................................................................... 163
5.1.1 Exception Handling Types and Priority ............................................................... 163
5.1.2 Timing of Exception Source Detection and Start of Exception Handling............ 164
5.1.3 Exception Vector Table ....................................................................................... 164
5.2 Power-on Reset ................................................................................................................. 167
5.3 Address Errors .................................................................................................................. 168
5.3.1 Address Error Sources ......................................................................................... 168
5.3.2 Address Error Exception Handling ...................................................................... 169
5.4 Interrupts ........................................................................................................................... 169
5.4.1 Interrupt Sources.................................................................................................. 169
5.4.2 Interrupt Priority .................................................................................................. 170
5.4.3 Interrupt Exception Handling............................................................................... 170
5.5 Instruction Exceptions....................................................................................................... 171
5.5.1 Types of Instruction Exception ............................................................................ 171
5.5.2 Trap Instruction.................................................................................................... 171
5.5.3 Slot Illegal Instructions ........................................................................................ 172
5.5.4 General Illegal Instructions .................................................................................. 172
5.6 Cases in Which Exceptions Are Not Accepted ................................................................. 173
5.6.1 After a Delayed Branch Instruction...................................................................... 173
5.6.2 After an Instruction for Which Interruption Is Prohibited.................................... 173
5.6.3 Instructions in Repeat Loops................................................................................ 174
5.7 Stack Status after Exception Handling .............................................................................. 175
5.8 Usage Notes ...................................................................................................................... 176
5.8.1 Stack Pointer (SP) Value...................................................................................... 176
5.8.2 Vector Base Register (VBR) Value ..................................................................... 176
5.8.3 Address Errors Occurring in Address Error Exception Handling Stacking ......... 176
Section 6 Interrupt Controller (INTC) ........................................................................... 177
6.1 Overview........................................................................................................................... 177
6.1.1 Features................................................................................................................ 177
6.1.2 Block Diagram ..................................................................................................... 178
6.1.3 Pin Configuration................................................................................................. 179
6.1.4 Register Configuration ......................................................................................... 179
Rev. 5.00 Sep 11, 2006 page xi of xxii