SH7065 Datasheet, PDF (540/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
• Data length: 8 bits
• Receive error detection: Overrun errors
• IrDA 1.0 compliance
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
In addition, the transmitter and receiver both have a 16-stage FIFO buffer structure, enabling
continuous serial data transmission and reception.
(However, IrDA communication is carried out in half-duplex mode.)
• Built-in baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
There are four interrupt sources—transmit-FIFO-data-empty, transmit-end, receive-FIFO-data-
full, and receive-error—that can issue requests independently. The transmit-FIFO-data-empty
and receive-FIFO-data-full interrupts can activate the on-chip DMAC to execute data transfer
• When not in use, the SCI can be stopped by halting its clock supply to reduce power
consumption.
• Choice of LSB-first or MSB-first mode
• In asynchronous mode, operation can be selected on a base clock of 4, 8, or 16 times the bit
rate.
Rev. 5.00 Sep 11, 2006 page 518 of 916
REJ09B0332-0500