SH7065 Datasheet, PDF (617/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit
data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
Simultaneous Multiple Receive Errors
If a number of receive errors occur at the same time, the state of the status flags in SC1SSR is as
shown in table 14.14. If there is an overrun error, data is not transferred from the receive shift
register (SCRSR) to the receive FIFO data register (SCFRDR), and the receive data is lost.
Table 14.14 SC1SSR Status Flags and Transfer of Receive Data
SC1SSR Status Flags
Receive Errors
RDF ORER FER PER
Overrun error
1
1
0
0
Framing error
0
0
1
0
Parity error
0
0
0
1
Overrun error + framing error
1
1
1
0
Overrun error + parity error
1
1
0
1
Framing error + parity error
0
0
1
1
Overrun error + framing error + 1
1
1
1
parity error
Legend:
O: Receive data is transferred from SCRSR to SCFRDR.
×: Receive data is not transferred from SCRSR to SCFRDR.
Receive Data Transfer
SCRSR → SCFRDR
×
O
O
×
×
O
×
Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set. Note that although the SCI stops transferring receive
data to SCFRDR after receiving a break, the receive operation continues, so if the FER and BRK
flags are cleared to 0 they will be set to 1 again.
Rev. 5.00 Sep 11, 2006 page 595 of 916
REJ09B0332-0500