SH7065 Datasheet, PDF (741/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.8 Port G
Port G is an input/output port with the 3 pins shown in figure 18.12.
Section 18 I/O Ports (I/O)
Port G
Expanded mode
with on-chip ROM disabled
PG31 (input/output) /
RxD2 (input/output)
PG30 (input/output) /
TxD2 (output)
PG29 (input/output) /
SCK2 (input)
Expanded mode
with on-chip ROM enabled
PG31 (input/output) /
RxD2 (input/output)
PG30 (input/output) /
TxD2 (output)
PG29 (input/output) /
SCK2 (input)
Single-chip
mode
PG31 (input/output) /
RxD2 (input/output)
PG30 (input/output) /
TxD2 (output)
PG29 (input/output) /
SCK2 (input)
Figure 18.12 Port G (PG31 to PG29)
18.8.1 Register Configuration
The port G register is shown in table 18.13.
Table 18.13 Port G Register
Name
Port G data register H
Abbreviation R/W
PGDRH
R/W
Initial Value Address
Access Size
H'0000
H'FFFF 1270 8, 16, 32
18.8.2 Port G Data Register H (PGDRH)
Bit: 15
14
13
12
11
10
9
8
PG31DR PG30DR PG29DR —
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Port G data register H (PGDRH) is a 16-bit readable/writable register that stores port G data. Bits
PG31DR to PG29DR correspond to pins PG31/RxD2 to PG29/SCK1.
Rev. 5.00 Sep 11, 2006 page 719 of 916
REJ09B0332-0500