SH7065 Datasheet, PDF (92/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction
Instruction Code
Operation
DMULU.L Rm,Rn
0011nnnnmmmm0101 Unsigned, Rn × Rm →
MACH, MACL
32 × 32 → 64 bits
DT
Rn
0100nnnn00010000 Rn – 1 → Rn;
when Rn = 0, 1 → T
When Rn ≠ 0, 0 → T
EXTS.B Rm,Rn
0110nnnnmmmm1110 Rm sign-extended
from byte → Rn
EXTS.W Rm,Rn
0110nnnnmmmm1111 Rm sign-extended
from word → Rn
EXTU.B Rm,Rn
0110nnnnmmmm1100 Rm zero-extended
from byte → Rn
EXTU.W Rm,Rn
0110nnnnmmmm1101 Rm zero-extended
from word → Rn
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed, (Rn) × (Rm) +
MAC → MAC
32 × 32 + 64 → 64 bits
MAC.W
@Rm+,@Rn+ 0100nnnnmmmm1111 Signed, (Rn) × (Rm) +
MAC → MAC
16 × 16 + 64 → 64 bits
MUL.L Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL
32 × 32 → 32 bits
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed, Rn × Rm →
MAC
16 × 16 → 32 bits
MULU.W Rm,Rn
0010nnnnmmmm1110 Unsigned, Rn × Rm →
MAC
16 × 16 → 32 bits
NEG
Rm,Rn
0110nnnnmmmm1011 0 – Rm → Rn
NEGC Rm,Rn
0110nnnnmmmm1010 0 – Rm – T → Rn,
borrow → T
SUB
Rm,Rn
0011nnnnmmmm1000 Rn – Rm → Rn
Execution
States T Bit
2–4^*
—
1
Comparison
result
1
—
1
—
1
—
1
—
3/(2–4)^* —
3/(2)^*
—
2–4^*
—
1–3^*
—
1–3^*
—
1
—
1
Borrow
1
—
Rev. 5.00 Sep 11, 2006 page 70 of 916
REJ09B0332-0500