SH7065 Datasheet, PDF (259/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bits 3 and 2—Read Cycle Column Address Output Cycle Interval Specification (DWR1,
DWR0): These bits specify the column address output cycle interval in a DRAM read cycle.
Description
Bit 3: DWR1
0
Bit 2: DWR0
0
In Normal
Read Cycle
In EDO
Read Cycle
In EDO Burst
Read Cycle
2 cycles (no waits)^* 2 cycles (no waits)^* 1 cycle (no waits)^*
1
3 cycles (1 wait) Do not set
Do not set
1
0
4 cycles (2 waits) Do not set
Do not set
1
5 cycles (3 waits) Do not set
Do not set
Note: * Initial value
Use the no wait setting for EDO DRAM.
Bits 1 and 0—Reserved: These bits are always read as 0 and should only be written with 0.
8.2.5 DRAM Control Register 2 (DCR2)
DRAM control register 2 (DCR2) is a 16-bit readable/writable register that specifies DRAM
control. Control is the same for CS4 and CS5 space accesses.
DCR2 is initialized to H'1FE0 by a power-on reset, but is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
DIW2
0
R/W
14
DIW1
0
R/W
13
DIW0
0
R/W
12
11
10
9
8
DDWW3 DDWW2 DDWW1 DDWW0 DDWR3
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
DDWR2 DDWR1 DDWR0 RDW TCAS
—
—
—
Initial value:
1
1
1
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R
R
R
Rev. 5.00 Sep 11, 2006 page 237 of 916
REJ09B0332-0500