SH7065 Datasheet, PDF (78/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction Formats
d type
15
xxxx xxxx
0
dddd dddd
d12 type 15
0
xxxx dddd dddd dddd
Source
Operand
Destination
Operand
dddddddd:
GBR
indirect with
displacement
R0 (register
direct)
R0 (register
direct)
dddddddd:
GBR
indirect with
displacement
dddddddd:
PC-relative with
displacement
R0 (register
direct)
dddddddd:
—
PC-relative
dddddddddddd: —
PC-relative
Sample
Instruction
MOV.L
@(disp,GBR),R0
MOV.L
R0,@(disp,GBR)
MOVA
@(disp,PC),R0
BF label
BRA label
(label=disp+PC)
nd8 type 15
0
xxxx nnnn dddd dddd
i type
15
0
xxxx xxxx i i i i i i i i
ni type
15
0
xxxx nnnn i i i i i i i i
dddddddd:
PC-relative with
displacement
iiiiiiii:
immediate
iiiiiiii:
immediate
iiiiiiii:
immediate
iiiiiiii:
immediate
nnnn: register
direct
Indexed GBR
indirect
R0 (register
direct)
—
nnnn: register
direct
MOV.L
@(disp,PC),Rn
AND.B
#imm,@(R0,GBR)
AND #imm,R0
TRAPA #imm
AD
#imm,Rn
Note: * In multiply and accumulate instructions, nnnn is the source register.
Rev. 5.00 Sep 11, 2006 page 56 of 916
REJ09B0332-0500