SH7065 Datasheet, PDF (252/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bit 15—Endian Specification (ENDIAN): Specifies the endian mode for each area.
Bit 15: ENDIAN
0
1
Description
Big-endian mode
Little-endian mode
(Initial value)
Bits 14 and 13—Memory Specification (TP1, TP0): These bits specify the type of memory or
I/O connected to each area.
Bit 14: TP1
Bit 13: TP0
Description
0
0
Access as normal space
(Initial value)
1
Reserved (Do not set)
1
0
Access as multiplexed address/data I/O space
1
Reserved (Do not set)
Note: Area 0 is always normal space. For this space, these bits are always read as 0 and should
only be written with 0.
Bit 12—External Wait Enable (EXWE): Specifies for each area whether or not wait requests via
the external WAIT pin are to be accepted.
Bit 12: EXWE
0
1
Description
External wait requests are accepted
External wait requests are not accepted
(Initial value)
Bit 11—Reserved: This bit is always read as 0 and should only be written with 0.
Bits 10 and 9—Bus Width Specification (SZ1, SZ0): These bits specify the bus width of each
area.
Bit 10: SZ1
Bit 9: SZ0
Description
0
0
Reserved (Do not set)
1
8 bits
1
0
16 bits
1
32 bits
(Initial value)
Note: In ROMless expanded mode, the bus width of the CS0 space is set by pins MD0 and MD1.
For details, see section 8.3.2, Areas.
Rev. 5.00 Sep 11, 2006 page 230 of 916
REJ09B0332-0500