SH7065 Datasheet, PDF (286/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Byte Access Control
Making the appropriate setting for the BAS bit in BCR enables byte-strobe type 16-bit-width
SRAM to be connected directly. When the BAS bit is cleared to 0, access is performed using the
WRHH, WRHL, WRLH, and WRLL signals. When the BAS bit is set to 1, access is performed
using the WR, HHBS, HLBS, LHBS, and LLBS signals. Also, since the HHBS, HLBS, LHBS,
and LLBS signals are also asserted in read accesses, it is always possible to know which byte
position is being accessed.
Figure 8.13 shows the timing for a 32-bit-bus-width, big-endian, no-wait write cycle, and figure
8.14 shows the timing for a read cycle.
Rev. 5.00 Sep 11, 2006 page 264 of 916
REJ09B0332-0500