SH7065 Datasheet, PDF (262/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.2.6 DRAM Control Register 3 (DCR3)
DRAM control register 3 (DCR3) is a 16-bit readable/writable register that specifies DRAM
control. Control is the same for CS4 and CS5 space accesses.
DCR3 is initialized to H'1800 by a power-on reset, but is not initialized in standby mode.
Bit: 15
BE
Initial value:
0
R/W: R/W
14
RSD
0
R/W
13
EDO
0
R/W
12
DSZ1
1
R/W
11
DSZ0
1
R/W
10
AMX2
0
R/W
9
AMX1
0
R/W
8
AMX0
0
R/W
Bit: 7
6
5
4
3
2
1
0
RFSH RMD
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R
R
R
R
R
R
Bit 15—Burst Enable (BE): Specifies whether or not burst access is performed on DRAM.
Bit 15: BE
0
1
Description
Burst disabled
Access in fast page mode
(Initial value)
Bit 14—RAS Down Mode (RSD): Specifies whether or not RAS down mode access is performed
on DRAM.
Bit 14: RSD
0
1
Description
DRAM accessed in RAS up mode
DRAM accessed in RAS down mode
(Initial value)
Bit 13—EDO Mode (EDO): Specifies whether or not EDO mode access is performed on DRAM.
Bit 13: EDO
0
1
Description
DRAM accessed in normal mode
DRAM accessed in EDO mode
(Initial value)
Rev. 5.00 Sep 11, 2006 page 240 of 916
REJ09B0332-0500