SH7065 Datasheet, PDF (525/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 12 Compare Match Timer (CMT)
Contention between CMCNT Word Write and Increment
If an increment pulse occurs in the T2 state of a CMCNT word write cycle, the counter write takes
precedence and counter is not incremented.
Figure 12.7 shows the timing in this case.
Pφ
Address
CMCNT write cycle
T1 T2
CMCNT
Internal write signal
CMCNT input clock
CMCNT
N
M
CMCNT write data
Figure 12.7 Contention between CMCNT Word Write and Increment
Rev. 5.00 Sep 11, 2006 page 503 of 916
REJ09B0332-0500