SH7065 Datasheet, PDF (350/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Table 9.3 Selecting External Request Mode with RS Bits
RS4 RS3 RS2 RS1 RS0 Address Mode Transfer Source
0
0
0
0
0
Dual address Any^*
mode
Transfer Destination
Any^*
0
0
0
1
0
Single address External memory or External device with
mode
memory-mapped DACK
external device
0
0
0
1
1
Single address External device with External memory or
mode
DACK
memory-mapped
external device
Note: * External memory, memory-mapped external device, on-chip memory, on-chip
peripheral module (except DMAC, UBC, and BSC)
On-Chip Peripheral Module Request Mode
In this mode a transfer is performed in response to a transfer request signal (interrupt request
signal) from one of the SH7065’s on-chip peripheral modules. As shown in table 9.4, there are a
total of 16 transfer request signals: six compare match interrupts or input capture interrupts from
the timer pulse unit (TPU), receive-data-full interrupts (RXI) and transmit-data-empty interrupts
(TXI) from the three serial communication interface (SCI) channels, A/D conversion end
interrupts (ADI) from the two A/D converter channels, and two interrupts from the motor
management timer (MMT). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE
= 0), DMA transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI receive-data-full
interrupt), the transfer source must be the SCI’s receive FIFO data register (SCFRDR). When the
transfer request is set to TXI (transfer request by SCI transmit-data-empty interrupt), the transfer
destination must be the SCI’s transmit FIFO data register (SCFTDR). When the transfer request is
set to ADIn, the transfer source must be the A/D data register (ADDRn).
To output a transfer request from an on-chip peripheral module, set the interrupt enable bit for the
module and output an interrupt signal.
When an on-chip peripheral module interrupt request signal is used as a DMA transfer request
signal, an interrupt is not issued to the CPU.
The transfer request signals shown in table 9.4 are cleared automatically when the corresponding
DMA transfer is performed. In cycle steal mode the signal is cleared for a single transfer; in burst
mode, there is a choice of clearance each time a transfer is executed or on execution of the last
Rev. 5.00 Sep 11, 2006 page 328 of 916
REJ09B0332-0500