SH7065 Datasheet, PDF (193/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

5.5 Instruction Exceptions
Section 5 Exception Handling
5.5.1 Types of Instruction Exception
There are three kinds of instruction that can initiate exception handling: the TRAP instruction, slot
illegal instructions, and general illegal instructions, These are summarized in table 5.8.
Table 5.8 Instruction Exception Types
Type
Trap instruction
Slot illegal instruction
General illegal
instruction
Source Instructions
Notes
TRAPA
Undefined code or instruction
that modifies PC located
immediately after delayed
branch instruction (in delay
slot)
Delayed branch instructions:
JMP, JSR, BRA, BSR, RTS, RTE,
BF/S, BT/S, BSRF, BRAF
Instructions that modify PC:
JMP, JSR, BRA, BSR, RTS, RTE, BT,
BF, TRAPA, BF/S, BT/S, BSRF, BRAF
Undefined code other than in
delay slot
5.5.2 Trap Instruction
When a TRAPA instruction is executed, trap instruction exception handling is started. The CPU
operates as follows.
1. The status register (SR) is saved on the stack.
2. The program counter (PC) is saved on the stack. The PC value saved is the start address of the
instruction following the trap instruction.
3. The exception service routine start address is fetched from the exception vector table entry
corresponding to the vector number specified by the TRAPA instruction, a jump is made to
that address, and program execution starts from that point. The jump in this case is not a
delayed branch.
Rev. 5.00 Sep 11, 2006 page 171 of 916
REJ09B0332-0500