SH7065 Datasheet, PDF (127/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Section 4 Clock Pulse Generator (CPG)
and Power-Down Modes
4.1 Overview
The SH7065 has an on-chip clock pulse generator (CPG) which is used to generate the clocks
supplied internally and control the power-down modes. In the power-down modes, the operation
of the on-chip peripheral modules and CPU, or of all functions, is halted. It is also possible to
select a division ratio for the clock supplied to individual modules, even during operation. These
features enable power consumption to be reduced.
4.1.1 Features
The CPG has the following features:
• Eight clock modes
Any of eight clock operating modes can be selected, differentiated by frequency range, power
consumption, and use of a crystal resonator or external clock input.
• Three clocks
The CPG can generate independently a master clock (CKM) used by the CPU, etc., a
peripheral clock (CKP) used by the peripheral modules, and an external bus clock (CKE) used
by the external bus interface.
• Frequency modification function
PLL (phase-locked loop) circuits and frequency dividers in the CPG enable the frequencies of
the master clock, peripheral clock, and external bus clock to be changed independently.
Frequency changes are performed by software in accordance with the settings in the frequency
control register (FRQCR).
The power-down modes include the following modes and functions:
• Power-down mode control
It is possible to stop the clock in sleep mode, software standby mode, and hardware standby
mode, to stop the clock supply to specific modules with the module standby function, and to
divide the frequency of clocks supplied to specific modules with the module clock division
function.
Rev. 5.00 Sep 11, 2006 page 105 of 916
REJ09B0332-0500