SH7065 Datasheet, PDF (546/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
14.2.4 Transmit FIFO Data Register (SCFTDR)
Bit: 7
6
5
4
3
2
1
0
R/W: W
W
W
W
W
W
W
W
The transmit FIFO data register (SCFTDR) is a 16-stage FIFO register (8 bits per stage) that stores
data for serial transmission.
If SCTSR is empty when transmit data has been written to SCFTDR, the SCI transfers the transmit
data written in SCFTDR to SCTSR and starts serial transmission.
SCFTDR is a write-only register, and cannot be read.
The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data
written in this case is ignored.
14.2.5 Serial Mode Register (SCSMR)
Bit: 7
C/A
Initial value:
0
R/W: R/W
6
5
4
3
2
CHR/ PE/ICK2 O/E/ICK1 STOP/ MP
ICK3
ICK0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
1
CKS1
0
CKS0
0
0
R/W
R/W
The serial mode register (SCSMR) is an 8-bit register used to set the SCI’s serial transfer format
and select the baud rate generator clock source. In IrDA communication mode, it is used to select
the output pulse width.
SCSMR can be read or written to by the CPU at all times.
SCSMR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the
SCI operating mode. In IrDA communication mode, this bit must be cleared to 0.
Bit 7: C/A
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
Rev. 5.00 Sep 11, 2006 page 524 of 916
REJ09B0332-0500