SH7065 Datasheet, PDF (555/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 7—Transmit FIFO Data Register Empty (TDFE): Indicates that data has been transferred
from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number
of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits
TTRG1 and TTRG0 in the FIFO control register (SCFCR), and transmit data can be written to
SCFTDR.
Bit 7: TDFE
Description
0
A number of transmit data bytes exceeding the transmit trigger set number
have been written to SCFTDR
[Clearing conditions]
• When transmit data exceeding the transmit trigger set number is written to
SCFTDR, and 0 is written to TDFE after reading TDFE = 1
• When transmit data exceeding the transmit trigger set number is written to
SCFTDR by the on-chip DMAC
1
The number of transmit data bytes in SCFTDR does not exceed the transmit
trigger set number
(Initial value)
[Setting conditions]
• In a reset, in standby mode
• When the number of SCFTDR transmit data bytes falls to or below the
transmit trigger set number as the result of a transmit operation^*
Note: * As SCFTDR is a 16-byte FIFO register, the maximum number of bytes that can be
written when TDFE = 0 is {16 – (transmit trigger set number)}. Data written in excess of
this will be ignored. The number of data bytes in SCFTDR is indicated by the upper 8
bits of SCFDR.
Rev. 5.00 Sep 11, 2006 page 533 of 916
REJ09B0332-0500