SH7065 Datasheet, PDF (401/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.2.2 Timer Mode Registers (TMDR)
Channel 0: TMDR0
Channel 3: TMDR3
Bit:
7
—
Initial value:
1
R/W: —
6
5
—
BFB
1
0
—
R/W
Section 10 16-Bit Timer Pulse Unit (TPU)
4
3
2
1
0
BFA
MD3
MD2
MD1
MD0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
MD3 MD2 MD1 MD0
Initial value:
1
1
0
0
0
0
0
0
R/W: —
—
—
—
R/W
R/W
R/W
R/W
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode and software standby mode. They
are not initialized by the module standby function.
TMDR settings should only be made when TCNT operation is halted.
Bits 7 and 6—Reserved: These bits are always read as 1 and cannot be modified.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Bit 5: BFB
0
1
Description
TGRB operates normally
TGRB and TGRD are used together for buffer operation
(Initial value)
Rev. 5.00 Sep 11, 2006 page 379 of 916
REJ09B0332-0500