SH7065 Datasheet, PDF (264/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bit 6: RMD
0
1
Description
CAS-before-RAS refreshing is performed
Self-refreshing is performed
(Initial value)
Bits 5 to 0—Reserved: These bits are always read as 0 and should only be written with 0.
8.2.7 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle, whether interrupts are to be generated, and if so the interrupt cycle.
RTCSR is initialized to H'0000 by a power-on reset, but is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
CMF
0
R/W
14
CMIE
0
R/W
13
CKS2
0
R/W
12
CKS1
0
R/W
11
CKS0
0
R/W
10
OVF
0
R/W
9
OVIE
0
R/W
8
LMTS1
0
R/W
Bit: 7
6
5
4
3
2
1
0
LMTS0 BREF2 BREF1 BREF0 TRAS2 TRAS1 TRAS0 —
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit 15—Compare Match Flag (CMF): Status flag that indicates a match between the refresh
timer counter (RTCNT) and refresh time constant register (RTCOR) values.
Bit 15: CMF
0
1
Description
RTCNT and RTCOR values do not match
(Initial value)
[Clearing condition]
When 0 is written to CMF after reading RTCSR when CMF = 1, or when
refreshing is performed with RFSH = 1 and RMD = 0 (CBR refreshing
performed)
RTCNT and RTCOR values match
[Setting condition]
When RTCNT = RTCOR
Rev. 5.00 Sep 11, 2006 page 242 of 916
REJ09B0332-0500