SH7065 Datasheet, PDF (330/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.1.3 Pin Configuration
Table 9.1 shows the pins provided for each DMAC channel.
Table 9.1 DMAC Pins
Pin Name
DMA transfer request
Abbreviation I/O
DREQn
Input
DMA transfer request
acceptance
DRAKn
Output
DMA transfer strobe
DACKn
Output
DMA transfer end
TENDn
Output
Function
DMA transfer request input from external
device to channel 0 or 1
Output of sampling acceptance signal for
DMA transfer request input to channel 0 or
1 from external device
Strobe output to external I/O in case of
DMA transfer request from external device
to channel 0 or 1
Output at end of DMA transfer on relevant
channel 0 or 1
9.1.4 Register Configuration
Table 9.2 summarizes the DMAC registers. The DMAC has a total of 33 registers. Eight registers
are allocated to each channel, and an additional control register is shared by all four channels.
Rev. 5.00 Sep 11, 2006 page 308 of 916
REJ09B0332-0500