SH7065 Datasheet, PDF (157/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.5 Output Clock Control
The CKIO and CK pins can be switched between clock output and the high-impedance state by
means of the CKIOOE and CKOE bits in the FRQCR register. The initial values depend on the
clock mode. Table 4.9 shows the correspondence between the clock mode, the state of the CKIO
and CK pins, and the initial value of the CKIOOE and CKOE bits.
When the CKIOOE and CKOE bits are modified, the CKIO or CK output is changed immediately.
Table 4.9 Clock Modes, CKIO and CK Pin States, and Initial Value of CKIOOE and
CKOE bits
Clock
Mode CKIO
Initial Pin State^*
CK
Initial Value
CKIOOE CKOE
Bit Value
Modification
CKIOOE CKOE
0
External clock output External clock output 1
1
Not
Possible
possible
1
External clock output External clock output 1
1
Not
Possible
possible
2
External clock output External clock output 1
1
Not
Possible
possible
3
External clock output External clock output 1
1
Not
Possible
possible
4
High impedance
External clock output 0
1
Possible Possible
5
High impedance
External clock output 0
1
Possible Possible
6
Clock input
External clock output 0
1
Not
Possible
possible
7
Clock input
External clock output 0
1
Not
Possible
possible
Note: * If hardware standby mode is entered after power is applied without executing a power-
on reset, the pin states will be undefined. In this case, the RES pin must be driven low
in hardware standby mode in order to fix the initial pin states according to the clock
mode. When hardware standby mode is entered after a power-on reset, the prior pin
states are retained.
Rev. 5.00 Sep 11, 2006 page 135 of 916
REJ09B0332-0500