SH7065 Datasheet, PDF (214/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
6.3.4 IRQ Status Register (ISR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit:
Initial value:
R/W:
7
IRQ7F
0
R/W
6
IRQ6F
0
R/W
5
IRQ5F
0
R/W
4
IRQ4F
0
R/W
3
IRQ3F
0
R/W
2
IRQ2F
0
R/W
1
IRQ1F
0
R/W
0
IRQ0F
0
R/W
The IRQ status register (ISR) is a 16-bit register that indicates the interrupt request status of
external interrupt input pins IRQ7 to IRQ0. When edge detection is set for an IRQ interrupt, an
interrupt request being retained can be cleared by reading IRQnF while set to 1 and then writing 0
to IRQnF.
ISR is initialized to H'0000 by a power-on reset. It is not initialized in standby mode.
Bits 15 to 8—Reserved: These bits are always read as 0 and cannot be modified.
Bits 7 to 0—IRQ0 to IRQ7 Flags (IRQ0F to IRQ7F): These bits indicate the IRQ7 to IRQ0
interrupt request status.
Rev. 5.00 Sep 11, 2006 page 192 of 916
REJ09B0332-0500