SH7065 Datasheet, PDF (496/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
TPDR
When writing to free
operation address
2Td
Compare output
waveform
Dead time generation
waveform
Output generation
waveform
PWM waveform
Figure 11.5 Example of PWM Waveform Generation
0% to 100% Duty Output
In the operating modes, PWM waveforms with any duty from 0% to 100% can be output. The
output PWM duty is set by means of the buffer registers (TBRU to TBRW).
100% duty output is performed when the buffer register (TBRU to TBRW) value is set to H'0000.
The waveform in this case has the positive phase in the 100% on state. 0% duty output is
performed when a value greater than the TPDR value is set as the buffer register (TBRU to
TBRW) value. The waveform in this case has the positive phase in the 100% off state.
External Counter Clear Function
In the operating modes, the TCNT counter can be cleared from an external source. When using the
counter clear function, the PCIO pin function should be set to input with the pin function
controller (PFC).
At the falling edge of PCIO, the TCNT counter is cleared to 2Td (initial set value), counts up until
it reaches the TPDR value, and then starts counting down. When the count reaches 2Td, TCNT
starts counting up again, and this sequence is repeated. An example of counter clearing is shown in
figure 11.6.
Rev. 5.00 Sep 11, 2006 page 474 of 916
REJ09B0332-0500