SH7065 Datasheet, PDF (571/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
14.2.10 FIFO Control Register (SCFCR)
Bit:
7
6
5
4
3
2
1
0
RTRG1 RTRG0 TTRG1 TTRG0 — TFRST RFRST LOOP
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
The FIFO control register (SCFCR) performs data count resetting and trigger data number setting
for the transmit and receive FIFO registers, and also contains a loopback test enable bit.
SCFCR can be read or written to at all times.
SCFCR is initialized to H'00 by a reset, by the module standby function, and in software standby
mode and hardware standby mode.
Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to
set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status 1
register (SC1SSR).
The RDF flag is set when the number of receive data bytes in the receive FIFO data register
(SCFRDR) is equal to or greater than the trigger set number shown in the following table.
Bit 7: RTRG1
0
1
Bit 6: RTRG0
0
1
0
1
Receive Trigger Number
1
4
8
14
(Initial value)
Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used
to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status 1 register (SC1SSR).
The TDFE flag is set when the number of transmit data bytes in the transmit FIFO data register
(SCFTDR) is equal to or less than the trigger set number shown in the following table.
Rev. 5.00 Sep 11, 2006 page 549 of 916
REJ09B0332-0500