SH7065 Datasheet, PDF (391/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the TPU.
Section 10 16-Bit Timer Pulse Unit (TPU)
Channel 3:
Channel 4:
Channel 5:
[I/O pins]
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC5A
TIOC5B
[Clock input]
Internal clock: Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Channel 0:
Channel 1:
Channel 2:
[I/O pins]
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
[Interrupt request signals]
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start
request signal
Figure 10.1 Block Diagram of TPU
[Interrupt request signals]
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Rev. 5.00 Sep 11, 2006 page 369 of 916
REJ09B0332-0500