SH7065 Datasheet, PDF (133/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
A clock with the frequency set by FRQCR (without phase coordination) is output from the CK
pin.
The CK pin can be set to the high-impedance state and a clock output from the CKIO pin by
means of settings in FRQCR.
Mode 6
An external clock is input from the CKIO pin, and PLL circuit 1 operates. The frequency
multiplication factor is fixed at 2. PLL circuit 2 is off.
When the CKE clock is multiplied by 1 by means of a setting in FRQCR, a CKE clock in phase
with the CKIO pin is output. When the CKE clock is multiplied by 1/2, the rise of the CKIO
output coincides with switching of the CKE clock. When the CKE clock is multiplied by 2,
switching of CKIO output coincides with the rise of the CKE clock.
A clock with the frequency set by FRQCR (without phase coordination) is output from the CK
pin.
The CK pin can be set to the high-impedance state by means of a setting in FRQCR.
Mode 7
An external clock is input from the CKIO pin, and PLL circuit 1 operates. The frequency
multiplication factor is fixed at 1. PLL circuit 2 is off.
When the CKE clock is multiplied by 1 by means of a setting in FRQCR, a CKE clock in phase
with the CKIO pin is output. When the CKE clock is multiplied by 1/2 or 1/4, the rise of the CKIO
output coincides with switching of the CKE clock.
A clock with the frequency set by FRQCR (without phase coordination) is output from the CK
pin.
The CK pin can be set to the high-impedance state by means of a setting in FRQCR.
Rev. 5.00 Sep 11, 2006 page 111 of 916
REJ09B0332-0500