SH7065 Datasheet, PDF (66/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Addressing Instruction
Mode
Format
Effective Address Calculation Method
Register
indirect with
displacement
@(disp:4,Rn) Effective address is register Rn contents
with 4-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Rn
disp
+
(zero-extended)
×
Rn +
disp × 1/2/4
Calculation
Formula
Byte: Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Indexed
register
indirect
@(R0,Rn)
1/2/4
Effective address is sum of register Rn and
R0 contents.
Rn
Rn + R0
+
Rn + R0
GBR indirect @(disp:8,
with
GBR)
displacement
R0
Effective address is register GBR contents
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
GBR
disp
+
(zero-extended)
×
GBR +
disp × 1/2/4
Byte: GBR + disp
Word:
GBR + disp × 2
Longword:
GBR + disp × 4
1/2/4
Rev. 5.00 Sep 11, 2006 page 44 of 916
REJ09B0332-0500