SH7065 Datasheet, PDF (51/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.2 DSR Register Bits
Bits
31–8
Name (Abbreviation)
Reserved
7
Signed Greater Than (GT)
6
Zero Value (Z)
5
Negative Value (N)
4
Overflow (V)
3–1
Condition Select (CS)
0
DSP Condition (DC)
Section 2 CPU
Function
0: Always read as 0.
The write value should also be 0.
Indicates that the operation result is positive (except
zero) or that operand 1 is greater than operand 2.
1: Operation result is positive or operand 1 is greater
than operand 2
Indicates that the operation result is zero (0) or that
operand 1 is equal to operand 2.
1: Operation result is zero (0) or operands are equal
Indicates that the operation result is negative or that
operand 1 is smaller than operand 2.
1: Operation result is negative or operand 1 is smaller
than operand 2
Indicates that the operation result has overflowed.
1: Operation result has overflowed
These bits specify the mode for selecting the operation
result status to be set in the DC bit.
Do not set these bits to 110 or 111.
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater than mode
101: Signed greater than or equal to mode
Sets the status of the operation result in the mode
specified by the CS bits.
0: Specified mode status has not occurred (false)
1: Specified mode status has occurred
Rev. 5.00 Sep 11, 2006 page 29 of 916
REJ09B0332-0500