SH7065 Datasheet, PDF (380/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Table 9.8 Contention between DMA and External Bus Release
Transfer Destination
External
Device with
DACK
External
Memory
Memory-
Mapped
External
Device
On-Chip
Memory
Transfer External
DMA transfer X
X
DMA transfer
source
device with not possible
not possible
DACK
External
X
memory
X
X
X
Memory-
X
mapped
external
device
X
X
X
On-chip
DMA transfer X
X
O
memory
not possible
On-chip
DMA transfer X
X
O
peripheral not possible
module
Legend:
O: DMA transfer possible while external bus is released
X: DMA transfer not possible while external bus is released
On-Chip
Peripheral
Module
DMA transfer
not possible
X
X
O
O
9.3.8 Chain Transfer
Use of chain transfer allows a specified block of data to be transferred consecutively without CPU
processing after the end of the current data transfer.
To perform chain transfer, it is necessary to set the registers used for chain transfer—the next
source address register (NSAR), next destination address register (NDAR), next transfer count
register (NDMATCR), and chain transfer count register (CHNCNT)—and to set the chain transfer
enable bit (CHNE) to 1 in the channel control register (CHCR). When the number of chain
transfers set in the transfer count register (DMATCR) are completed while chain transfer is
enabled, in the state following the end of transfer the set values are copied from NSAR into SAR,
from NDAR into DAR, and from NDMATCR into DMATCR, and the DMAC waits for the next
transfer request (figure 9.2). However, whether or not copying of NSAR and NDAR is necessary
can be specified by means of the next source address register enable bit (NSARE) and next
destination address register enable bit (NDARE) in CHCR. Register copying is performed the
number of times set in the chain transfer count register (CHNCNT), and chain transfer ends when
Rev. 5.00 Sep 11, 2006 page 358 of 916
REJ09B0332-0500