SH7065 Datasheet, PDF (363/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority Order
When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to
channel 0, which has a higher priority, the channel 0 transfer is started immediately.
If fixed mode has been set for the priority order (CH0 > CH1), or if burst mode is set for channel
0, transfer on channel 1 is continued after transfer on channel 0 is completely finished.
If round robin mode has been set for the priority order, transfer on channel 1 is restarted after one
transfer unit of data is transferred on channel 0, regardless of whether cycle steal mode or burst
mode is set for channel 0. Bus mastership then alternates in the order: channel 1 → channel 0 →
channel 1 → channel 0.
Since channel 1 is in burst mode, the bus is not given to the CPU during this period, regardless of
whether fixed mode or round robin mode is set for the priority order.
An example of round robin mode operation is shown in figure 9.11.
CPU DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 CPU
CPU
DMAC CH1
Burst mode
DMAC CH0 and CH1
Round robin mode
DMAC CH1
Burst mode
Priority system: Round robin mode
Channel 0: Cycle steal mode
Channel 1: Burst mode
Figure 9.11 Bus Handling with Two DMAC Channels Operating
CPU
Rev. 5.00 Sep 11, 2006 page 341 of 916
REJ09B0332-0500