SH7065 Datasheet, PDF (443/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.5 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower-16-bit TCNT is in phase counting mode.
Table 10.6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 10.6 Cascading Combinations
Combination
Channels 1 and 2
Channels 4 and 5
Upper 16 Bits
TCNT1
TCNT4
Lower 16 Bits
TCNT2
TCNT5
Example of Cascaded Operation Setting Procedure
Figure 10.21 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
1
Set external pin function 2
Start count operation 3
1. Set bits TPSC2 to TPSC0 in the
channel 1 (channel 4) TCR to B'111 to
select TCNT2 (TCNT5)
overflow/underflow counting.
2. Set the external pin function with the pin
function controller (PFC).
3. Set the CST bit in TSTR for the upper
and lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 10.21 Cascaded Operation Setting Procedure
Rev. 5.00 Sep 11, 2006 page 421 of 916
REJ09B0332-0500