SH7065 Datasheet, PDF (316/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
In the software standby state, external bus address/data/bus control signals (except DRAM signals)
go to the high-impedance state, that is, the bus-released state. In the software standby state, the
BREQ bus release request input signal is ignored. Note that the following two cases apply to the
BACK bus use enable output signal.
1. Transition from bus-released state (BREQ input asserted low) to software standby state
When the bus release request signal (BREQ) is asserted low in the normal state, the BACK pin
is set to low output, indicating that the bus has been released. If the software standby state is
entered in this state, BACK output goes high, but other address, data, and bus control signals
remain in the high-impedance state, that is, the bus-released state. If the software standby state
is exited while BREQ input is still asserted, BACK output goes low and the bus-released state
is maintained. If software standby is exited while BREQ input is negated, BACK output goes
high and the chip returns to the normal state (in which the bus is not released).
2. Transition from normal state (BREQ input negated high) to software standby state
When a transition is made from the normal state to the software standby state, BACK output
goes to the Z (high-impedance) state, and the external bus goes to the high-impedance state,
that is, the bus-released state. If this state is exited while BREQ input is negated, BACK output
returns to the high level. If BREQ input is in the asserted state when software standby is
exited, BACK is output high for 1.5 external clock (CKE) cycles, and then returns to the low
level, that is, the bus-released state.
When DMAC transfer is specified without regard to transfer space or transfer mode during
execution of a TAS instruction (unless the destination of TAS instruction execution is on-chip
RAM), DMA transfer cycles are inserted between a read and write cycles of the TAS
instruction. In this case, if the bus release request signal BREQ is asserted, bus authority is
released. All of the DMAC channels should be stopped before the execution of a TAS
instruction, when the bus release request can be occurred during execution of the TAS
instruction. (BREQ is not accepted during execution of a TAS instruction unless DMA transfer
cycles occur during the execution of the TAS instruction.)
Rev. 5.00 Sep 11, 2006 page 294 of 916
REJ09B0332-0500