SH7065 Datasheet, PDF (442/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
When TGR is an input capture register: Figure 10.20 shows an operation example in which
TGRA has been designated as an input capture register, and buffer operation has been designated
for TGRA and TGRC.
Counter clearing by input capture has been set for TCNT, and both rising and falling edges have
been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'0532
Figure 10.20 Example of Buffer Operation (2)
H'09FB
H'0F07
Rev. 5.00 Sep 11, 2006 page 420 of 916
REJ09B0332-0500