SH7065 Datasheet, PDF (465/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing
Figure 10.43 shows the timing of setting of the TCFV flag in TSR by overflow occurrence, and
the TCIV interrupt request signal timing.
Figure 10.44 shows the timing of setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 10.43 TCIV Interrupt Setting Timing
Pφ
TCNT input
clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 10.44 TCIU Interrupt Setting Timing
Rev. 5.00 Sep 11, 2006 page 443 of 916
REJ09B0332-0500