SH7065 Datasheet, PDF (364/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States
When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 8,
Bus State Controller (BSC).
DREQ Pin Sampling and DRAK Signal
In external request mode, the DREQ pin for each channel is sampled using falling edge or low
level detection. The DREQ sampling circuit for each channel comprises a noise canceler and edge
detection circuit, a 16-stage FIFO, and a 1-stage FIFO.
Regardless of whether DREQ pin falling edge detection or low level detection is used, the signal is
sampled via a noise canceler circuit. The noise canceler eliminates noise of one clock cycle or less
in duration by ignoring the first clock cycle of DREQ input.
After passing through the noise canceler, an external request signal is sampled by one of three
DREQ sampling methods, as selected by the relevant register settings: falling edge detection, low
level detection using the 16-stage FIFO, or low level detection using the 1-stage FIFO.
Whichever DREQ sampling method is selected, the DRAK signal is output for one CKE state each
time DREQ is sampled. Regardless of whether cycle steal or burst mode is selected, and of the
DREQ sampling method, the DRAK signal is output when generation of a DMA transfer cycle in
response to the sampled DREQ signal is confirmed. DRAK signal output is synchronized with
CKE, but it is not possible to stipulate the output timing relative to the external bus cycle.
• DREQ falling edge detection
When DREQ falling edge detection is used, DREQ samples are not stored in a FIFO, and
DMA transfer is carried out in response to a single falling edge. Since the noise canceler
function ignores the first state of DREQ input, the DREQ signal must be input for at least two
states. DREQ sampling is performed in the same way regardless of whether single or dual
address mode, or cycle steal or burst mode, is selected.
With DREQ falling edge detection, the number of transfers to be initiated by detection of a
single falling edge can be set, regardless of whether single or dual address mode, or cycle steal
or burst mode, is selected. The following settings can be made with the Flag Clear Timing
Select (FCS) bit in the channel control register (CHCR) for each channel.
Rev. 5.00 Sep 11, 2006 page 342 of 916
REJ09B0332-0500