SH7065 Datasheet, PDF (48/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Special load/store instructions are provided for accessing the RS, RE, and MOD registers. For
example, the coding for accessing the RS register is as follows.
LDC Rm,RS;
LDC.L @Rm+,RS;
STC RS,Rn;
STC.L RS,@-Rn;
Rm → RS
(Rm) → RS, Rm+4 → Rm
RS → Rn
Rn-4 → Rn, RS → (Rn)
The instructions for setting an address in the RS and RE registers for zero-overhead repeat control
are as follows.
LDRS @(disp,PC);
LDRE @(disp,PC);
disp × 2 + PC → RS
disp × 2 + PC → RE
The GBR and VBR registers are the same as the previous SuperH microcomputer registers. In the
SH7065, four control bits (DMX, DMY, RF1, and RF0) and an RC counter have been added to the
SR register, and the RS, RE, and MOD registers are provided as new registers.
2.1.3 System Registers
There are four 32-bit system registers: the multiply and accumulate register high (MACH),
multiply and accumulate register low (MACL), procedure register (PR), and program counter
(PC).
MACH and MACL store the results of multiply or multiply and accumulate operations*, PR stores
the return destination address of a subroutine procedure, and PC shows the executing program
address and controls the processing flow. PC shows the address 4 bytes ahead of the currently
executing instruction. These registers are the same as the SuperH microcomputer registers.
Note: * These registers are used only when executing an instruction supported by the SH-1 and
SH-2. They are not used with the new multiply instruction provided in the SH-DSP
(PMULS).
Rev. 5.00 Sep 11, 2006 page 26 of 916
REJ09B0332-0500