SH7065 Datasheet, PDF (572/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)^*
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: * Initial value. Figures in parentheses are the number of empty bytes in SCFTDR when
the flag is set.
Bit 3—Reserved: This bit is always read as 0 and should only be written with 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the
transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST
Description
0
Reset operation disabled^*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a reset or in standby mode.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
Description
0
Reset operation disabled^*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a reset or in standby mode.
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD) and receive
output pin (RxD), enabling loopback testing.
Bit 0: LOOP
0
1
Description
Loopback test disabled
Loopback test enabled
(Initial value)
Rev. 5.00 Sep 11, 2006 page 550 of 916
REJ09B0332-0500