SH7065 Datasheet, PDF (171/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
• MCLK152 to MCLK000
Bit nn2:
MCLKnn2
0
Bit nn1:
MCLKnn1
0
Bit nn0:
MCLKnn0
0
1
1
0
1
1
0
0
1
1
0
1
Description
Clock supplied to module is not divided
(Initial value in clock modes 1, 3, 5, 6)
Clock supplied to module is further divided by 2
Clock supplied to module is further divided by 3
Clock supplied to module is further divided by 5
Reserved (Do not set)
Reserved (Do not set)
Clock supplied to module is further divided by 8
Clock supplied to module is further divided by 64
(Initial value in clock modes 0, 2, 4, 7)
4.10 Sleep Mode
4.10.1 Transition to Sleep Mode
If a SLEEP instruction is executed when the SBY bit in SBYCR is cleared to 0, the chip switches
from the program execution state to sleep mode. After execution of the SLEEP instruction, the
CPU halts but its register contents are retained. The on-chip peripheral modules continue to
operate, and clocks continue to be output from the CKIO and CK pins. In sleep mode, external bus
release requests are not accepted.
The CPU regards the SBYCR write as being executed in one cycle, and performs the next
processing. However, the write actually takes the number of cycles shown in table 8.12 in section
8, Bus State Controller (BSC). To ensure that the value written from the CPU to SBYCR is
reliably reflected in the SLEEP instruction, either read SBYCR or else wait for the number of
cycles shown in table 8.12, before executing the SLEEP instruction.
4.10.2 Exit from Sleep Mode
Sleep mode is exited by means of an interrupt (NMI, IRQ, IRL, or on-chip peripheral module), a
DMAC address error, a power-on reset, or the HSTBY pin.
Exit by Interrupt: When an NMI, IRQ, IRL, or on-chip peripheral module interrupt is generated,
sleep mode is exited and interrupt exception handling is executed. The interrupt request is not
accepted and sleep mode is not exited when the priority level of the generated interrupt is not
Rev. 5.00 Sep 11, 2006 page 149 of 916
REJ09B0332-0500