SH7065 Datasheet, PDF (432/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.7 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
CST bit
Time
TCFV
Figure 10.7 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs cyclic count operation. The TGR register for setting the cycle is designated as an
output compare register, and counter clearing by compare match is selected by means of bits
CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as
a cyclic counter when the corresponding bit in TSTR is set to 1. When the count value matches the
value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.
After a compare match, TCNT starts counting up again from H'0000.
Figure 10.8 illustrates cyclic counter operation.
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
Time
CST bit
TGF
Flag cleared by software
or DMAC activation
Figure 10.8 Cyclic Counter Operation
Rev. 5.00 Sep 11, 2006 page 410 of 916
REJ09B0332-0500