SH7065 Datasheet, PDF (230/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
bits, the setting of the least significant bit of UBAMRH and UBAMRL is invalid. When XYE is 1,
either XAB or YAB must be selected with the XYS bit in UBBR.
UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in hardware standby
mode. They are not initialized by the module standby function or in software standby mode.
XYE
0
1
UBAMRH
CAB31–16/IAB31–16 masked
XAB15–1 masked (XYS = 0)
UBAMRL
CAB15–0/IAB15–0 masked
YAB15–1 masked (XYS = 1)
Bits 15 to 0:
UBMn
0
1
Note: n = 31 to 0
Description
User break address UBAn is included in break conditions
User break address UBAn is not included in break conditions
(Initial value)
7.2.3 User Break Bus Cycle Register (UBBR)
Bit: 15
14
13
12
11
10
9
8
UBIE
—
—
—
—
—
XYE
XYS
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
CP1
CP0
ID1
ID0
RW1 RW0
SZ1
SZ0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets five
conditions—(1) internal bus (C-bus) or internal bus (I-bus)/X memory bus or Y memory bus, (2)
CPU cycle/DMA cycle, (3) instruction fetch/data access, (4) read/write, and (5) operand size
(byte/word/longword)—and selects whether or not a user break interrupt is to generated when a
condition is matched. UBBR is initialized to H'0000 by a power-on reset and in hardware standby
mode. It is not initialized by the module standby function or in software standby mode.
Rev. 5.00 Sep 11, 2006 page 208 of 916
REJ09B0332-0500