SH7065 Datasheet, PDF (343/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.2.6 Next Destination Address Registers 0 to 3 (NDAR0 to NDAR3)
Bit: 31 30 29 28 27 26 25 24 23
0
............................
Initial value: — — — — — — — — — ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} R/W
Next destination address registers 0 to 3 (NDAR0 to NDAR3) are 32-bit readable/writable
registers that specify the destination address for the next transfer when chain transfer is set. In
single address mode, the NDAR value is ignored when a device with DACK has been specified as
the transfer destination.
Specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit
transfer. Operation cannot be guaranteed if a different address is set.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
9.2.7 Next Transfer Count Registers 0 to 3 (NDMATCR0 to NDMATCR3)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Next transfer count registers 0 to 3 (NDMATCR0 to NDMATCR3) are 32-bit readable/writable
registers that specify the transfer count for the next transfer on the channel (number of bytes,
words, or longwords) in chain transfer.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
Rev. 5.00 Sep 11, 2006 page 321 of 916
REJ09B0332-0500