SH7065 Datasheet, PDF (236/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
7.4 Examples of Use
CPU Instruction Fetch Cycle Break Condition Settings
Example of Valid Settings:
• Register settings
UBARH = H'0000, UBARL = H'0404
UBAMRH = H'0000, UBAMRL = H'0000
UBBR = H'8054
• Set conditions
Address: H'00000404; address mask: H'00000000
Bus cycle: CPU, instruction fetch, read (operand size not included)
A user break interrupt is generated after execution of the instruction at address H'00000404.
Example of Invalid Settings:
• Register settings
UBARH = H'0015, UBARL = H'389C
UBAMRH = H'0000, UBAMRL = H'0000
UBBR = H'8058
• Set conditions
Address: H'0015389C; address mask: H'00000000
Bus cycle: CPU, instruction fetch, write (operand size not included)
As an instruction fetch cycle is not a write cycle, a user break interrupt is not generated.
CPU Data Access Cycle (Internal Bus (C-Bus) Cycle) Break Condition Settings
Example of Valid Settings (1):
• Register settings
UBARH = H'0012, UBARL = H'3456
UBAMRH = H'0000, UBAMRL = H'0000
UBBR = H'806A
• Set conditions
Address: H'00123456; address mask: H'00000000
Bus cycle: CPU, data access, write, word
A user break interrupt is generated when word data is written to address H'00123456.
Rev. 5.00 Sep 11, 2006 page 214 of 916
REJ09B0332-0500