SH7065 Datasheet, PDF (366/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
• DREQ low level detection using 1-stage FIFO
DREQ low level sampling using the 1-stage FIFO should be selected when external bus cycles
are two CKE states or longer in maximum-speed operation. If external bus cycles are two CKE
states or longer in maximum-speed operation, when DREQ input is halted upon DRAK signal
output, one subsequent DMA transfer will always be performed after the DMA transfer cycle
corresponding to this DRAK signal output before transfer is halted (figure 9.19). If low level
detection using the 1-stage FIFO is selected when the external bus cycle is one CKE state in
maximum-speed operation, the amount of DMA cycle overrun cannot be guaranteed.
With the 1-stage FIFO, as with the 16-stage FIFO, DREQ sampling is performed at the rise of
CKE. The noise canceler function prevents sampling of DREQ input at the first rise of CKE.
The sampled DREQ signal is stored in the 1-stage FIFO, and the FIFO is full after one sample
is taken. The DRAK signal is output at the same time as, or earlier than, address output in the
corresponding DMA transfer cycle, and is output once for each DREQ sample.
The sampling conditions for the 1-stage FIFO are different from those for the 16-stage FIFO.
With the 16-stage FIFO, FIFO incrementing and decrementing are performed simultaneously
(see figure 9.19), but with the 1-stage FIFO, after the FIFO is cleared by decrementing, the
next sampling operation is performed. The FIFO decrement timing is the same as the DRAK
signal output timing. Figure 9.19 shows an example of the operation when single/burst mode
DMA transfer is carried out with DREQ sampling by low level detection using the 1-stage
FIFO. In figure 9.19, when DREQ input is halted (B in the figure) at the point at which DRAK
is output (A in the figure), transfer is terminated after execution of the DMA transfer cycle
following the corresponding DMA cycle. With this DREQ sampling method, sampling is
carried out in the same way regardless of whether single or dual address mode, or cycle steal or
burst mode, is selected (figures 9.20 to 9.22).
Rev. 5.00 Sep 11, 2006 page 344 of 916
REJ09B0332-0500