SH7065 Datasheet, PDF (346/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit 1—NMI Flag (NMIF): Flag that indicates NMI input. Setting of this bit can be performed
regardless of whether the DMAC is operating or halted. If this bit is set during data transfer,
transfers on all channels are suspended. The CPU cannot write a 1 to NMIF. This bit can only be
cleared by writing 0 after reading 1.
Bit 1: NMIF
0
1
Description
No NMI input, DMA transfer enabled
[Clearing condition]
When 0 is written to NMIF after reading NMIF = 1
NMI input, DMA transfer disabled
[Setting condition]
When an NMI interrupt is generated
(Initial value)
Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME
bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is
enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are
suspended.
Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMIF or AE bit in DMAOR is 1.
Bit 0: DME
0
1
Description
Operation disabled on all channels
Operation enabled on all channels
(Initial value)
9.3 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order. It ends the transfer when the transfer end conditions are
satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. There are two modes for DMA transfer: single address mode and dual
address mode. Either burst mode or cycle steal mode can be selected as the bus mode.
Rev. 5.00 Sep 11, 2006 page 324 of 916
REJ09B0332-0500