SH7065 Datasheet, PDF (345/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bits 11 to 8—Round Robin Channel Select 3 to 0 (RC3 to RC0): When there are simultaneous
transfer requests for a number of channels, these bits determine the channel priority order for
executing the transfers. Bits RC3 to RC0 correspond to channels CH3 to CH0. When a bit is set to
1, the priority of the corresponding channel is determined according to the round robin method.
Bits 11 to 8:
RCn
Description
0
The priority order of corresponding channel CHn (n = 0 to 3) is fixed. When all
RC bits are 0, the channel priority order is CH0 > CH1 > CH2 > CH3.
(Initial value)
1
The priority order of corresponding channel CHn (n = 0 to 3) is determined
according to the round robin method.
Note:
When the round robin method is set for the priority order, at least two RC bits should be set
to 1. If only one RC bit is set to 1, the inter-channel priority order will be CH0 > CH1 > CH2
> CH3.
When the priority order of two or more channels is determined by the round robin method,
channels with consecutive channel numbers must be set (e.g. CH2 and CH3, or CH1, CH2,
and CH3). Operation cannot be guaranteed if channels with non-consecutive channel
numbers (such as CH0 and CH2) are designated as having their priority order determined
by the round robin method.
If round robin priority is specified for CH1, CH2, and CH3, the channel priority relationship
with the other channel will be as follows:
CH0 > CH1, CH2, CH3.
Round Robin
Bits 7 to 3—Reserved: These bits are always read as 0 and cannot be modified.
Bit 2—Address Error Flag (AE): Flag that indicates the occurrence of an address error during
DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended. The
CPU cannot write a 1 to AE. This bit can only be cleared by writing 0 after reading 1.
Bit 2: AE
0
1
Description
No address error, DMA transfer enabled
[Clearing condition]
When 0 is written to AE after reading AE = 1
Address error, DMA transfer disabled
[Setting condition]
When an address error is caused by the DMAC
(Initial value)
Rev. 5.00 Sep 11, 2006 page 323 of 916
REJ09B0332-0500