SH7065 Datasheet, PDF (428/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Bit n: SYNCn
0
1
Note: n = 5 to 0
Description
TCNTn operates independently (TCNT presetting/clearing is unrelated to other
channels)
(Initial value)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
10.3 Interface to Bus Master
10.3.1 16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these
registers can be read and written to in 16-bit units.
These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.
An example of 16-bit register access operation is shown in figure 10.2.
Internal data bus
H
Bus master L
Bus
interface
Module
data bus
TCNTH
TCNTL
Figure 10.2 16-Bit Register Access Operation (Bus Master ↔ TCNT (16 Bits))
10.3.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit registers. As the data bus to the CPU is 16 bits
wide, these registers can be read and written to in 16-bit units. They can also be written to in 8-bit
units.
Examples of 8-bit register access operation are shown in figures 10.3, 10.4, and 10.5.
Rev. 5.00 Sep 11, 2006 page 406 of 916
REJ09B0332-0500