SH7065 Datasheet, PDF (258/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bit 13: TPCS2
0
:
1
Bit 12: TPCS1
0
1
:
1
Bit 11: TPCS0
0
1
0
:
0
1
Description
Cycles specified by TPC + 0 cycles
(Initial value)
Cycles specified by TPC + 1 cycle
Cycles specified by TPC + 2 cycles
:
Cycles specified by TPC + 6 cycles
Cycles specified by TPC + 7 cycles
Bits 10 to 8—RAS-CAS Delay specification (RCD2 to RCD0): These bits specify the DRAM
RAS-CAS delay time.
Bit 10: RCD2 Bit 9: RCD1 Bit 8: RCD0
0
0
0
1
:
:
:
1
1
0
1
Note: Use the one cycle setting for EDO DRAM.
Description
Normal Access
EDO Access
1 cycle (Initial value) 1 cycle (Initial value)
2 cycles
Do not set
:
:
7 cycles
Do not set
8 cycles
Do not set
Bits 7 and 6—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 5 and 4—Write Cycle Column Address Output Cycle Interval Specification (DWW1,
DWW0): These bits specify the column address output cycle interval in a DRAM write cycle.
Description
Bit 5: DWW1
0
Bit 4: DWW0
0
In Normal
Write Cycle
In EDO
Write Cycle
In EDO Burst
Write Cycle
2 cycles (no waits)^* 2 cycles (no waits)^* 1 cycle (no waits)^*
1
3 cycles (1 wait)
Do not set
Do not set
1
0
4 cycles (2 waits) Do not set
Do not set
1
5 cycles (3 waits) Do not set
Do not set
Note: * Initial value
Use the no wait setting for EDO DRAM.
Rev. 5.00 Sep 11, 2006 page 236 of 916
REJ09B0332-0500