SH7065 Datasheet, PDF (166/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.9 Register Descriptions
4.9.1 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit readable/writable register that specifies the
power-down mode status.
SBYCR is initialized to H'1F by a power-on reset, but is not initialized in software standby mode.
Bit: 7
6
5
4
3
2
1
0
SBY
HIZ
—
—
—
—
—
—
Initial value:
0
0
0
1
1
1
1
1
R/W: R/W
R/W
R
R
R
R
R
R
Bit 7—Software Standby (SBY): Specifies a transition to software standby mode. The SBY bit
cannot be set to 1 while the watchdog timer (WDT) is operating (while the timer enable bit (TME)
is set to 1 in the watchdog timer’s timer control/status register (TCSR)). When making a transition
to software standby mode, the watchdog timer must be stopped by clearing the TME bit to 0
before the SBY bit is set.
Bit 7: SBY
0
1
Description
Transition to sleep mode on execution of SLEEP instruction (Initial value)
Transition to software standby mode on execution of SLEEP instruction
Bit 6—Port High Impedance (HIZ): Selects whether specific output pins retain their state or
become high-impedance in software standby mode. See appendix B, Pin States, for the pins that
are controlled. The HIZ bit cannot be set to 1 when the TME bit is set to 1 in the watchdog timer’s
TCSR register. To set output pins to the high-impedance state, the TME bit must be cleared to 0
before the HIZ bit is set.
Bit 6: HIZ
0
1
Description
Pin state retained in software standby mode
Pins go to high-impedance state in software standby mode
(Initial value)
Bit 5—Reserved: This bit is always read as 0 and should only be written with 0.
Bits 4 to 0—Reserved: These bits are always read as 1 and should only be written with 1.
Rev. 5.00 Sep 11, 2006 page 144 of 916
REJ09B0332-0500